The present invention relates to methods and apparatus for reducing leakage current in a disabled silicon-on-insulator (SOI) circuit.
Large scale integrated circuits are being designed to accommodate an ever increasing number of circuits in order to achieve higher and higher functionality. For example, digital circuits (or analog circuits) are being designed with very high numbers of gates and other functional circuitry to meet processing objectives in the marketplace. As the complexity of integrated circuits (ICs) continue to increase, however, the number of transistors and other components used to implement the circuitry also increases and the probability of a faulty component or circuit occurring in an IC approaches one. The existence of a faulty circuit or component may require that the IC be discarded.
It has been proposed to use redundant circuits on the IC in order to permit replacement of the circuitry containing a faulty component. For example, FIG. 1 illustrates an IC 10 employing digital circuit A, digital circuit B, digital circuit C, and digital circuit D, where one or more of the circuits may be redundant. Thus, even when a fault occurs, the IC 10 may be salvaged by enabling the redundant circuit. This can increase the IC yield and save the IC manufacturer a considerable amount of money. While the redundant circuit(s) may be activated and used in place of the faulty components, the faulty component may be deactivated. Conventional techniques for activating good circuits and deactivating faulty circuits include blowing fuses, such as electrical fuses (e-fuses) and/or laser-trimmed fuses.
The components or circuits of an IC may be faulty due to improper fabrication. For example, an imperfection may have been present on the substrate during fabrication or the fabrication procedure itself may be faulty. Improperly fabricated ICs may be discovered during IC testing, prior to packaging. If a faulty component is discovered on an IC during pre-packaging IC testing, the faulty component may be deactivated and a redundant circuit activated to take its place through the blowing of certain fuses, preferably, laser fuses since access to the IC is possible because the IC has yet to be packaged.
ICs may also be damaged after the pre-packaging IC testing. The components or circuits of an IC may be faulty due to damage during the packaging of the IC, for example, when the die is cut from the wafer, when the wafer is cleaned, when the die is bonded to the packaging, and so forth. ICs that become faulty due to packaging are usually not discovered until post-packaging testing. Since the packaging of an IC can be a considerable amount of the overall cost of manufacturing the IC, simply discarding a faulty IC could be expensive. A conventional technique proposes the use of additional redundant circuits that can be activated in place of the faulty components discovered in post-packaging IC testing. These additional redundant circuits can be activated through the use of electrical fuses (e-fuses), rather than laser fuses, since direct access to the IC is not possible. This can permit the use of a packaged IC that would have otherwise been discarded.
In order to minimize the complexity of the power and clock distribution networks of the IC, the redundant circuitry usually shares common power and clock distribution networks with the other circuits of the IC. Thus, in the majority of IC the redundant circuitry is being actively clocked and powered although it is not being used. This can increase power consumption of the IC. Similarly, when a circuit containing a fault is disabled, it is still actively clocked and powered, which also contributes to the power consumption problem.
U.S. Patent Publication 2005-0036259, which is incorporated herein by reference, addresses the power consumption problem by proposing to gate the signaling and power to the redundant circuitry, such that the unused redundant circuitry does not receive clock signals or power. The decision as to whether to enable or disable the signaling and power to the unused redundant circuitry is based on the state of fuses used to enable/disable the redundant circuitry.
Unfortunately, the gating of clock signals and power (as well as other signaling) to unused redundant circuitry of an IC is not always practical or desirable. Thus, another technique to permit enabling and disabling of circuitry on an IC is needed that limits unnecessary power dissipation by disabled circuitry.